ESD and EOS
By LearnESD.com Team

Technology is moving fast. Consumers want their Electronic gadget or instrument to work faster and smaller in size. As a result, the electronic chips used inside this gadget and instrument are required to be smaller and faster. The density of electronic circuits inside the chips increased and this increase complexity make the electronic chips more susceptible to Electrostatic Discharge (ESD) damage.

An protection network is commonly placed inside Integrated Circuits (ICs) to provide protection against 2kV HBM, 200V MM and 1kV CDM.
There are also many electronic chips without the protection and with withstand voltage threshold less than 1kV.
These withstand voltage thresholds decrease tremendously as technology becomes more advanced.

The requirement for a thinner oxide layer, a narrower metal lines, a shallower junction and a denser circuitry in smaller electronic chips does not only cause them to be more susceptible to damage but it also makes them more easily to be damaged by electrical overstress.

These electronic chips are electrically over-stressed (EOS) when their current or voltage is exceeding their operational rating.

The damages on the electrically over-stressed electronic chips are visible to human's eyes. The electronic chips have either outer physical damages (e.g. package crack or damage) or internal visual damages (e.g. bonding wire fuse open, carbonised mold on the electronic chip's die surface).

These electrically over-stressed devices will show open and short electrical signatures when tested.

Some of the electronic chips that are already wounded by will still pass the final testing at the assembly plant and some will show leakage current.

Electronic chips that are killed by event through the transfer of static charges between two bodies at different electrical potential in split of second normally show invisible physical damages on the die surfaces. De-layering process on the die is required in order to see the damage spot.

Failure on electronic chips can be analysed by using techniques such as Liquid Crystal that focus on hot spot detection to locate the leakage current that is due to events and Scanning Electron Microscope (SEM) to spot the damage location at high magnification after de-layering process done on the die. Pinhole or oxide punch and junction damage are common failure modes observed in electronic chips that are killed by events.

Simulate the failure by using HBM, MM and CDM test models to replicate the observed failure signature and failure mode is definitely a recommended way to understand failure mechanism.




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